User guide

Parameter Name Options Description
Enable rx_clkout port On
Off
When you turn on this parameter, the rx_
clkout port is enabled. Refer to the clock and
reset signals section for more information about
this port.
Enable Hard PRBS support On
Off
When you turn on this parameter, you enable
the Hard PRBS data generation and checking
logic in the Native PHY.
Reference clock frequency 644.53125 MHz
322.265625 MHz
Specifies the input reference clock frequency.
The default is 322.265625 MHz.
Enable additional control and
status pins
On
Off
When you turn this option on, the core includes
the rx_block_lock and rx_hi_ber ports.
Include FEC sublayer On
Off
When you turn on this parameter, the core
includes logic to implement FEC and a soft
10GBASE-R PCS.
Set FEC_ability bit on power up
and reset
On
Off
When you turn on this parameter, the core sets
the Assert KR FEC Ability bit (0xB0[16])
FEC ability bit during power up and reset,
causing the core to assert the FEC ability. This
option is required for FEC functionality.
Set FEC_Enable bit on power up
and reset
On
Off
When you turn on this parameter, the core sets
the KR FEC Request bit (0xB0[18]) during
power up and reset, causing the core to request
the FEC ability during Auto Negotiation. This
option is required for FEC functionality.
10GBASE-R Parameters
The 10GBASE-R parameters specify basic features of the 10GBASE-R PCS. The FEC options also allow
you to specify the FEC ability.
Table 2-101: 10GBASE-R Parameters
Parameter Name Options Description
10GbE Reference clock frequency 644.53125 MHz
322.265625 MHz
Specifies the input reference clock frequency.
The default is 322.265625 MHz.
1G Reference clock frequency 125 MHz Specifies the input reference clock frequency.
125 MHz is the only option.
Enable additional control and
status pins
On
Off
When you turn on this parameter, the core
includes the rx_block_lock and rx_hi_ber
ports.
2-130
10GBASE-R Parameters
UG-01143
2015.05.11
Altera Corporation
Implementing Protocols in Arria 10 Transceivers
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