User guide

Figure 2-53: Reconfiguration Block Details
PCS
Controller
TX EQ Controller
DFE Controller
CTLE Controller
PMA Controller
rcfg_data
rcfg_data
rcfg_data
(1)
rcfg_data
Avalon-MM
Decoder
Avalon-MM Bus
Avalon-MM Bus
Avalon-MM Bus
Avalon-MM reconfig_busy Signal
HSSI
Reconfiguration
Requests
MGMT_CLK
(2)
PCS
Reconfiguration
Interface
PMA
Reconfiguration
Interface
Notes:
1. rcfg = Reconfiguration
2. MGMT_CLK = Management Clock
Related Information
• Arria 10 Enhanced PCS Architecture on page 5-18
• Arria 10 Standard PCS Architecture on page 5-37
Parameterizing the 10GBASE-KR PHY
The Arria 10 1G/10GbE and 10GBASE-KR PHY IP core allows you to select either the Backplane-KR or
1Gb/10Gb Ethernet variant. When you select the Backplane-KR variant, the Link Training (LT) and
Auto Negotiation (AN) tabs appear. The 1Gb/10Gb Ethernet variant (1G/10GbE) does not implement
the LT and AN functions.
Complete the following steps to parameterize the 10GBASE-KR PHY IP core in the parameter editor:
1. Instantiate the Arria 10 1G/10GbE and 10GBASE-KR PHY from the IP Catalog.
Refer to Select and Instantiate the PHY IP Core on page 2-2.
2. Select Backplane-KR from the IP variant list located under Ethernet MegaCore Type.
3. Use the parameter values in the tables in 10GBASE-R Parameters on page 2-130, 10GBASE-KR
Auto-Negotiation and Link Training Parameters on page 2-131, and 10GBASE-KR Optional
Parameters on page 2-132 as a starting point. You can then modify the setting to meet your specific
requirements.
4. Click Generate HDL to generate the 10GBASE-KR PHY IP core top-level HDL file.
2-128
Parameterizing the 10GBASE-KR PHY
UG-01143
2015.05.11
Altera Corporation
Implementing Protocols in Arria 10 Transceivers
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