User guide

The 10GBASE-KR PHY IP core includes the following components:
Standard and Enhanced PCS Datapaths
The Enhanced PCS and PMA inside the Native PHY are configured to be the 10GBASE-R PHY. Refer to
the Standard PCS and Enhanced PCS architecture chapters for more details on how these blocks support
1G, 10G protocols and FEC.
Auto Negotiation, IEEE 802.3 Clause 73
The auto negotiation (AN) is needed to synchronize the start time of the link training on both sides of the
link partners. This ensures that the link training can be done effectively within the 500 ms of the specified
timeframe as required.
Link Training (LT), IEEE 802.3 Clause 72
Arria 10 devices have soft link training IP that complies with the IEEE 802.3 Clause 72 standard training
procedure. This IP includes:
• training frame lock that is different from the regular 64b/66b frame_lock
• training frame generation
• the control channel codec
• Local Device (LD) coefficient update
• Link Partner (LP) coefficient generation
Reconfiguration Block
The Reconfiguration Block performs Avalon-MM writes to the PHY for both PCS and PMA reconfigura‐
tion. The Avalon-MM master accepts requests from the PMA or PCS controller. It performs the Read-
Modify-Write or Write commands on the Avalon-MM interface. The PCS controller receives rate change
requests from the Sequencer and translates them to a series of Read-Modify-Write or Write commands to
the PMA and PCS.
Eight compile-time configuration modes are supported. The configuration modes include one set of four
with reference clock at 322 MHz and one set of four with reference clock at 644 MHz. Each set of four
consists of all combinations of FEC sublayer on/off.
UG-01143
2015.05.11
10GBASE-KR Functional Description
2-127
Implementing Protocols in Arria 10 Transceivers
Altera Corporation
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