User guide

The following table shows the typical expected resource utilization for selected configurations using the
Quartus II software v15.0 for Arria 10 devices. The numbers of ALMs and logic registers are rounded up
to the nearest 100.
Table 2-99: 10GBASE-KR PHY Performance and Resource Utilization
Variant ALMs ALUTs Registers M20K
10GBASE-KR PHY 2400 3750 3100 1
10GBASE-KR PHY with FEC 2400 3750 3100 1
10GBASE-KR Functional Description
The following figure shows the supporting components inside the 10GBASE-KR PHY IP core.
Figure 2-52: 10GBASE-KR PHY IP Core Block Diagram
Registers
GbE
PCS
1588
FIFO
Auto-Negotiation
Clause 73
Link Training
Clause 72
HSSI Reconfiguration
Requests
1588
FIFO
GbE
PCS
Native PHY
Standard RX PCS
TX PMA
RX PMA
40/32
40/32
rx_pld_clk rx_pma_clk
Standard TX PCS
tx_pld_clk tx_pma_clk
Enhanced TX PCS
tx_pld_clk tx_pma_clk
Enhanced RX PCS
rx_pld_clk rx_pma_clk
Divide by 33/1/2
Avalon-MM
8 + 2
64 + 8
TX_GMII_DATA
XGMII_TX_CLK
TX_XGMII_DATA
TX_PMA_CLKOUT
RX_XGMII_DATA
64 + 8
8 + 2
XGMII_RX_CLK
RX_GMII_DATA
32
64 + 8
Soft Logic Hard Logic
Register
Access
Nios II LT Interface
64 + 8
Nios II Sequencer
Interface
10GBASE-KR PHY IP
Unused
Note: The 10GBASE-KR PHY IP core does not support backplane applications with IEEE 1588 Precision
Time Protocol.
2-126
10GBASE-KR Functional Description
UG-01143
2015.05.11
Altera Corporation
Implementing Protocols in Arria 10 Transceivers
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