User guide

Figure 2-48: Block Lock Assertion
This figure shows the assertion on rx_enh_blk_lock signal when the Receiver detects the block
delineation.
0707070707070707h
FFh
0h 1h
0100009C0100009Ch 0707070707070707h
11h FFh
rx_ready
0h 1h
tx_parallel_data
tx_control
rx_parallel_data
rx_control
rx_enh_highber
rx_enh_block_lock
The following figures show Idle insertion and deletion.
Figure 2-49: IDLE Word Insertion
This figure shows the insertion of IDLE words in the receiver data stream.
Idle Inserted
Before Insertion
After Insertion
FD000000000004AEh BBBBBB9CDDDDDD9Ch 0707070707070707h 00000000000000FBh
FD000000000004AEh BBBBBB9CDDDDDD9Ch 00000000000000FBh AAAAAAAAAAAAAAAAhrx_parallel_data
rx_parallel_data
Figure 2-50: IDLE Word Deletion
This figure shows the deletion of IDLE words from the receiver data stream.
00000000000004ADh 00000000000004AEh
0707070707FD0000h 000000FB07070707h
00000000000004ADh 00000000000004AEh
0707070707FD0000h
AAAAAAAA000000FBh
Idle Deleted
Before Deletion
After Deletion
rx_parallel_data
rx_parallel_data
Figure 2-51: OS Word Deletion
This figure shows the deletion of Ordered set word in the receiver data stream.
OS Deleted
Before Deletion
After Deletion
FD000000000004AEh 000000FBDDDDDD9Ch AAAAAAAA00000000h 00000000AAAAAAAAh
FD000000000004AEh DDDDDD9CDDDDDD9Ch 00000000000000FBh AAAAAAAAAAAAAAAAh
rx_parallel_data
rx_parallel_data
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Native PHY IP Ports for 10GBASE-R and 10GBASE-R with IEEE 1588v2...
UG-01143
2015.05.11
Altera Corporation
Implementing Protocols in Arria 10 Transceivers
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