User guide

Parameter Range
Enable embedded JTAG AVMM
master
On
Off
Table 2-96: Configuration Files Parameters
Parameter Range
Configuration file prefix
—
Generate SystemVerilog package file On
Off
Generate C header file On
Off
Generate MIF (Memory Initialization
File)
On
Off
Table 2-97: Generation Options Parameters
Parameter Range
Generate parameter documentation
file
On
Off
Native PHY IP Ports for 10GBASE-R and 10GBASE-R with IEEE 1588v2 Transceiver Configurations
Figure 2-47: High BER
This figure shows the rx_enh_highber status signal going high when there are errors on the
rx_parallel_data output.
1122334455667788h 1122324455667788h 112233405566F788h 1122334455667788h
00h
1122334455667788h
00h
0h 1h
tx_parallel_data
tx_control
rx_parallel_data
rx_control
rx_enh_highber
UG-01143
2015.05.11
Native PHY IP Ports for 10GBASE-R and 10GBASE-R with IEEE 1588v2...
2-123
Implementing Protocols in Arria 10 Transceivers
Altera Corporation
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