User guide

Parameter Range
Selected CDR reference clock
frequency
322.265625 MHz and 644.53125 MHz
PPM detector threshold
62.5, 100,125, 200, 250, 300, 500, 1000
CTLE adaptation mode
Manual
Triggered
Decision feedback equalization mode disabled
Table 2-90: Enhanced PCS Parameters
Parameter Range
Enhanced PCS/PMA interface width 32, 40, 64
Note: 10GBASE-R with KR FEC allows 64 only.
FPGA fabric/Enhanced PCS interface
width
66
Enable RX/TX FIFO double-width
mode
Off
TX FIFO mode • Phase Compensation (10GBASE-R and 10GBASE-R with
KR FEC)
• Register (10GBASE-R with 1588)
TX FIFO partially full threshold 11
TX FIFO partially empty threshold 2
RX FIFO mode • 10GBASE-R (10GBASE-R and 10GBASE-R with KR FEC)
• Register (10GBASE-R with 1588)
RX FIFO partially full threshold
23
RX FIFO partially empty threshold
2
Table 2-91: 64B/66B Encoder and Decoder Parameters
Parameter Range
Enable TX 64B/66B encoder On
Enable RX 64B/66B decoder On
UG-01143
2015.05.11
Native PHY IP Parameter Settings for 10GBASE-R, 10GBASE-R with IEEE...
2-121
Implementing Protocols in Arria 10 Transceivers
Altera Corporation
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