User guide

Figure 2-45: Connection Guidelines for a 10GBASE-R or 10GBASE-R with FEC PHY Design
Reset
Controller
Arria 10 Transceiver
Native PHY
To MAC/RS
through XGMII
Interface
64d + 8c
PLL IP
Medium
Figure 2-46: Connection Guidelines for a 10GBASE-R with IEEE 1588v2 PHY Design
Reset
Controller
To MAC/RS
through XGMII
Interface
64d + 8c
64d + 8c
FIFO in the
FPGA core
for TX
FIFO in the
FPGA core
for RX
PLL IP
Medium
Arria 10 Transceiver
Native PHY
8. Simulate your design to verify its functionality.
Related Information
• Arria 10 Enhanced PCS Architecture on page 5-18
For more information about Enhanced PCS architecture
• Arria 10 PMA Architecture on page 5-1
For more information about PMA architecture
• Using PLLs and Clock Networks on page 3-49
For more information about implementing PLLs and clocks
• PLLs on page 3-3
PLL architecture and implementation details
• Resetting Transceiver Channels on page 4-1
Reset controller general information and implementation details
• Enhanced PCS Ports on page 2-54
For detailed information about the available ports in the 10GBASE-R 1588 protocol.
UG-01143
2015.05.11
How to Implement 10GBASE-R, 10GBASE-R with IEEE 1588v2, and 10GBASE-R...
2-119
Implementing Protocols in Arria 10 Transceivers
Altera Corporation
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