User guide

Figure 2-44: Signals and Ports of Native PHY IP Core for the 10GBASE-R, 10GBASE-R with IEEE 1588v2,
and 10GBASE-R with FEC
Generating the IP core creates signals and ports based on your parameter settings.
reconfig_reset
reconfig_clk
reconfig_avmm
tx_digital_reset
xgmii_tx_c[7:0] (2)
xgmii_tx_d[63:0] (2)
xgmii_tx_clk
1’b1 (1)
tx_control[17:0]
tx_parallel_data[127:0]
tx_coreclkin
tx_clkout
tx_enh_data_valid
tx_fifo_flags
Reconfiguration
Registers
TX Enhanced PCS
rx_clkout
rx_coreclkin
rx_enh_blk_lock
rx_enh_highber
rx_fifo_flags
RX Enhanced PCS
Nios Hard
Calibration IP
TX PMA
Serializer
RX PMA
DeserializerCDR
tx_cal_busy
rx_cal_busy
tx_serial_data
rx_serial_data
rx_parallel_data[127:0]
rx_control[19:0]
rx_cdr_refclk0
rx_is_lockedtodata
rx_is_lockedtoref
Clock
Generation
Block
tx_serial_clk0 (from TX PLL)
tx_analog_reset
rx_analog_reset
rx_digital_reset
xgmii_rx_clk
Arria 10 Transceiver Native PHY
Notes:
1. For 10GBASE-R with 1588 configurations, this signal is user-controlled.
2. For 10GBASE-R with 1588 configurations, this signal is connected from the output of TX FIFO in the FPGA fabric.
5. Instantiate and configure your PLL.
6. Create a transceiver reset controller. You can use your own reset controller or use the Arria 10
Transceiver Native PHY Reset Controller IP.
7. Connect the Arria 10 Transceiver Native PHY to the PLL IP and the reset controller.
2-118
How to Implement 10GBASE-R, 10GBASE-R with IEEE 1588v2, and 10GBASE-R...
UG-01143
2015.05.11
Altera Corporation
Implementing Protocols in Arria 10 Transceivers
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