User guide

Related Information
Arria 10 Enhanced PCS Architecture on page 5-18
For more information about the Enhanced PCS Architecture
How to Implement 10GBASE-R, 10GBASE-R with IEEE 1588v2, and 10GBASE-R with FEC in Arria 10
Transceivers
Before you begin
You should be familiar with the 10GBASE-R and PMA architecture, PLL architecture, and the reset
controller before implementing the 10GBASE-R, 10GBASE-R with IEEE 1588v2, or 10GBASE-R with
FEC Transceiver Configuration Rules.
You must design your own MAC and other layers in the FPGA to implement the 10GBASE-R, 10GBASE-
R with 1588, or 10GBASE-R with KR FEC Transceiver Configuration Rule using the Native PHY IP.
1. Instantiate the Arria 10 Transceiver Native PHY IP from the IP Catalog.
Refer to Select and Instantiate the PHY IP Core on page 2-2 for more details.
2. Select 10GBASE-R, 10GBASE-R 1588, or 10GBASE-R with KR FEC from the Transceiver configu‐
ration rule list located under Datapath Options, depending on which protocol you are implementing.
3. Use the parameter values in the tables in Native PHY IP Parameter Settings for 10GBASE-R,
10GBASE-R with IEEE 1588v2, and 10GBASE-R with FEC as a starting point. Or, you can use the
protocol presets described in Presets. You can then modify the settings to meet your specific require‐
ments.
4. Click Generate to generate the Native PHY IP core RTL file.
UG-01143
2015.05.11
How to Implement 10GBASE-R, 10GBASE-R with IEEE 1588v2, and 10GBASE-R...
2-117
Implementing Protocols in Arria 10 Transceivers
Altera Corporation
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