User guide

• Data acquisition
• Test equipment
• Measurement
The protocol is applicable to systems communicating by local area networks including, but not limited to,
Ethernet. The protocol enables heterogeneous systems that include clocks of various inherent precision,
resolution, and stability to synchronize to a grandmaster clock.
Figure 2-40: Transceiver Channel Datapath and Clocking for 10GBASE-R with IEEE 1588v2
Transmitter Enhanced PCSTransmitter PMA
Receiver PMA
Receiver Enhanced PCS
TX
Gearbox
tx_serial_data
Serializer
Interlaken
Disparity Generator
Scrambler
(self sync) mode
Parallel Clock
PRBS
Generator
PRP
Generator
rx_serial_data
Deserializer
CDR
Descrambler
Interlaken
Disparity Checker
Block
Synchronizer
Interlaken
Frame Sync
RX
Gearbox
PRBS
Verifier
Transcode
Decoder
KR FEC RX
Gearbox
KR FEC
Decoder
KR FEC
Block Sync
KR FEC
Descrambler
Parallel Clock
Parallel Clock
Serial Clock
Parallel and Serial Clocks
Clock Divider
Parallel and Serial Clocks
Clock Generation Block (CGB)
Serial Clock
Input Reference Clock
ATX PLL
fPLL
CMU PLL
64B/66B Decoder
and RX SM
10GBASE-R
BER Checker
PRP
rx_pma_div_clkout
tx_pma_div_clkout
Verifier
rx_coreclkin
rx_clkout
Register Mode
Interlaken
Frame Generator
Interlaken
CRC32 Generator
Interlaken
CRC32 Checker
64B/66B Encoder
and TX SM
FPGA
Fabric
tx_coreclkin
tx_clkout
KR FEC
TX Gearbox
KR FEC
Scrambler
KR FEC
Encoder
Transcode
Encoder
10.3125 Gbps
5156.25 MHz (data rate/2) (1)
Notes:
1. Value based on the clock division factor chosen.
2. Value calculated as data rate / PCS-PMA interface width.
40
66
@ 257.8125 MHz (2)
TX XGMII
@ 156.25 MHz
RX XGMII
@ 156.25 MHz
@ 257.8125 MHz (2)
40
66
64
64
Soft Phase
Compensation
FIFO
Soft Clock
Compensation
FIFO
64 (data) + 8 (control)
Register Mode
64 (data) + 8 (control)
10GBASE-R with FEC
Arria 10 10GBASE-R has the optional FEC variant that also targets the 10GBASE-KR PHY. This provides
a coding gain to increase the link budget and BER performance on a broader set of backplane channels as
defined in Clause 69. It provides additional margin to account for variations in manufacturing and
environment conditions. The additional TX FEC sublayer:
• Receives data from the TX PCS
• Transcodes 64b/66b words
• Performs encoding/framing
• Scrambles and sends the FEC data to the PMA
UG-01143
2015.05.11
10GBASE-R, 10GBASE-R with IEEE 1588v2, and 10GBASE-R with FEC Variants
2-113
Implementing Protocols in Arria 10 Transceivers
Altera Corporation
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