User guide

Figure 2-39: Transceiver Channel Datapath and Clocking for 10GBASE-R
Transmitter Enhanced PCSTransmitter PMA
Receiver PMA
Receiver Enhanced PCS
TX
Gearbox
tx_serial_data
Serializer
Interlaken
Disparity Generator
Scrambler
(self sync) mode
Parallel Clock
PRBS
Generator
PRP
Generator
rx_serial_data
Deserializer
CDR
Descrambler
Interlaken
Disparity Checker
Block
Synchronizer
Interlaken
Frame Sync
RX
Gearbox
PRBS
Verifier
Transcode
Decoder
KR FEC RX
Gearbox
KR FEC
Decoder
KR FEC
Block Sync
KR FEC
Descrambler
Parallel Clock
Parallel Clock
Serial Clock
Parallel and Serial Clocks
Clock Divider
Parallel and Serial Clocks
Clock Generation Block (CGB)
Serial Clock
Input Reference Clock
ATX PLL
fPLL
CMU PLL
64B/66B Decoder
and RX SM
10GBASE-R
BER Checker
PRP
rx_pma_div_clkout
tx_pma_div_clkout
Verifier
rx_coreclkin
rx_clkout
Enhanced PCS
TX FIFO
(3)
Enhanced PCS
RX FIFO
(4)
Interlaken
Frame Generator
Interlaken
CRC32 Generator
Interlaken
CRC32 Checker
64B/66B Encoder
and TX SM
TX
Data &
Control
RX
Data &
Control
FPGA
Fabric
tx_coreclkin
tx_clkout
KR FEC
TX Gearbox
KR FEC
Scrambler
KR FEC
Encoder
Transcode
Encoder
10.3125 Gbps
5156.25 MHz (data rate/2) (1)
Notes:
1. Value based on the clock division factor chosen.
2. Value calculated as data rate / PCS-PMA interface width.
3. This block is in Phase Compensation mode for the 10GBASE-R configuration and register mode for the 10GBASE-R with 1588 configuration.
4. This block is in 10GBASE-R mode for the 10GBASE-R configuration and register mode for the 10GBASE-R with 1588 configuration.
40
66
@ 257.8125 MHz (2)
64 + 8
@ 156.25 MHz
from XGMII
64 + 8
@ 156.25 MHz
from XGMII
@ 257.8125 MHz (2)
40
66
64
64
10GBASE-R with IEEE 1588v2
When choosing the 10GBASE-R PHY with IEEE 1588v2 mode preset, the hard TX and RX FIFO are set to
register mode. The output clock frequency of tx_clkout and rx_clkout to the FPGA fabric is based on
the PCS-PMA interface width. For example, if the PCS-PMA interface is 40-bit, tx_clkout and
rx_clkout run at 10.3125 Gbps/40-bit = 257.8125 MHz.
The 10GBASE-R PHY with IEEE 1588v2 creates the soft TX phase compensation FIFO and the RX clock
compensation FIFO in the FPGA core so that the effective XGMII data is running at 156.25 MHz
interfacing with the MAC layer.
The IEEE 1588 Precision Time Protocol (PTP) is supported by the preset of the Arria 10 transceiver
Native PHY that configures 10GBASE-R PHY IP in IEEE-1588v2 mode. PTP is used for precise synchro‐
nization of clocks in applications such as:
• Distributed systems in telecommunications
• Power generation and distribution
• Industrial automation
• Robotics
2-112
10GBASE-R, 10GBASE-R with IEEE 1588v2, and 10GBASE-R with FEC Variants
UG-01143
2015.05.11
Altera Corporation
Implementing Protocols in Arria 10 Transceivers
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