User guide

Parameters Value
RX word aligner mode Synchronous state machine
RX word aligner pattern length 7, 10
RX word aligner pattern (hex)
0x000000000000007c (Comma) (for 7-
bit aligner pattern length),
0x000000000000017c (/K28.5/) (for 10-
bit aligner pattern length)
Number of word alignment patterns to achieve sync 3
Number of invalid data words to lose sync 3
Number of valid data words to decrement error count 3
Enable fast sync status reporting for deterministic latency
SM
On/Off
Enable rx_std_wa_patternalign port Off
Enable rx_std_wa_a1a2size port Off
Enable rx_std_bitslipboundarysel port Off
Enable rx_bitslip port Off
Enable TX bit reversal Off
Enable TX byte reversal Off
Enable TX polarity inversion On/Off
Enable tx_polinv port On/Off
Enable RX bit reversal Off
Enable rx_std_bitrev_ena port Off
Enable RX byte reversal Off
Enable rx_std_byterev_ena port Off
Enable RX polarity inversion On/Off
Enable rx_polinv port On/Off
Enable rx_std_signaldetect port On/Off
All options under PCIe Ports Off
10GBASE-R, 10GBASE-R with IEEE 1588v2, and 10GBASE-R with FEC Variants
10GBASE-R PHY is the Ethernet-specific physical layer running at a 10.3125-Gbps data rate as defined in
Clause 49 of the IEEE 802.3-2008 specification. Arria 10 transceivers can implement 10GBASE-R variants
like 10GBASE-R with IEEE 1588v2, and with forward error correction (FEC).
2-110
10GBASE-R, 10GBASE-R with IEEE 1588v2, and 10GBASE-R with FEC Variants
UG-01143
2015.05.11
Altera Corporation
Implementing Protocols in Arria 10 Transceivers
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