User guide

Parameters Value
FPGA fabric / Standard RX PCS interface width 10
TX FIFO mode
low latency (for GbE)
register_fifo (for GbE with IEEE 1588v2)
RX FIFO mode
low latency (for GbE)
register_fifo (for GbE with IEEE 1588v2)
Enable Standard PCS low latency mode Off
Enable tx_std_pcfifo_full port On/Off
Enable tx_std_pcfifo_empty port On/Off
Enable rx_std_pcfifo_full port On/Off
Enable rx_std_pcfifo_empty port On/Off
TX byte serializer mode Disabled, Serialize x2 , Serialize x4
RX byte deserializer mode Disabled, Deserialize x2 , Deserialize x4
Enable TX 8B/10B encoder On
Enable TX 8B/10B disparity control On/Off
Enable RX 8B/10B decoder On/Off
RX rate match FIFO mode
gige (for GbE)
disabled (for GbE with IEEE 1588v2)
RX rate match insert / delete -ve pattern (hex)
0x000ab683 (/K28.5/D16.2/) (for GbE)
0x00000000 (for GbE with IEEE 1588v2)
RX rate match insert / delete +ve pattern (hex)
0x000a257c (/K28.5/D16.2/) (for GbE)
0x00000000 (for GbE with IEEE 1588v2)
Enable rx_std_rmfifo_full port On/Off
Enable rx_std_rmfifo_empty port On/Off
PCI Express Gen3 rate match FIFO mode Bypass
Enable TX bit slip Off
Enable tx_std_bitslipboundarysel port On/Off
UG-01143
2015.05.11
Native PHY IP Parameter Settings for GbE and GbE with IEEE 1588v2
2-109
Implementing Protocols in Arria 10 Transceivers
Altera Corporation
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