User guide

Figure 1-6: Arria 10 GX Devices with 12 Transceiver Channels and One PCIe Hard IP Block
Transceiver
Bank
GXBL1D
Transceiver
Bank
GXBL1C
Transceiver
Bank
Transceiver
Bank
GX 048 EF29
GX 032 EF29
GX 027 EF29
GX 032 EF27
GX 027 EF27
GX 022 EF29
GX 022 EF27
GX 016 EF29
GX 016 EF27
CH5
CH4
CH3
CH2
CH1
CH0
Transceiver
Bank
Note:
(1) These devices have transceivers only on the left hand side of the device.
Legend:
PCIe Gen1 - Gen3 HIP blocks with Configuration via Protocol (CvP) capabilities.
Arria 10 GX device with 12 transceiver channels and one PCIe Hard IP block.
PCIe
Gen1 - Gen3
Hard IP
(with CvP)
Figure 1-7: Arria 10 GX Devices with 6 Transceiver Channels and One PCIe Hard IP Block
Transceiver
Bank
GXBL1C Transceiver
Bank
PCIe Hard IP
GX 022 CU19
GX 016 CU19
CH5
CH4
CH3
CH2
CH1
CH0
Transceiver
Bank
GXBL1C
Note:
(2) These devices have transceivers only on the left hand side of the device.
Legend:
PCIe Gen1 - Gen3 Hard IP block with Configuration via Protocol (CvP) capabilities.
Arria 10 GX device with six transceiver channels and one PCIe Hard IP block.
(1)
(1) Only CH5 and CH4 support PCIe Hard IP block with CvP capabilities.
Related Information
• Arria 10 Avalon-ST Interface for PCIe Datasheet
• Arria 10 Avalon-MM Interface for PCIe Datasheet
• Arria 10 Avalon-MM DMA Interface for PCIe Datasheet
• Arria 10 Avalon-ST Interface with SR-IOV for PCIe Datasheet
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Arria 10 GX Device Transceiver Layout
UG-01143
2015.05.11
Altera Corporation
Arria 10 Transceiver PHY Overview
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