User guide

Figure 2-27: Transceiver Channel Datapath and Clocking at 1250 Mbps for GbE, GbE with IEEE 1588v2
RX
FIFO (1)
Byte
Deserializer (4)
8B/10B Decoder
Rate Match FIFO (2)
Receiver PMA
Word Aligner
Deserializer
CDR
Receiver Standard PCS
Transmitter Standard PCS
Transmitter PMA
Serializer
tx_serial_data
rx_serial_data
FPGA
Fabric
TX
FIFO (1)
Byte Serializer (3)
8B/10B Encoder
PRBS
Generator
TX Bit Slip
/2
/2
Parallel Clock
Serial Clock
Parallel and Serial Clock
Parallel and Serial Clock
Clock Divider
rx_pma_div_clkout
Serial Clock
Clock Generation Block (CGB)
ATX PLL
CMU PLL
fPLL
tx_coreclkin
rx_coreclkin
rx_clkout or
tx_clkout
Parallel Clock
(Recovered)
Parallel Clock
(From Clock
Divider)
tx_clkout
tx_clkout
tx_clkout
rx_clkout
PRBS
Verifier
tx_pma_div_clkout
10
625 MHz
125 MHz
10
625 MHz
125 MHz
Notes:
1. This block is set in low latency mode for GbE and register_fifo mode for GbE with IEEE 1588v2.
2. The rate match FIFO of the hard PCS is disabled for GbE with IEEE 1588v2 because it is not able to acheive deterministic latency. It is also disabled for Triple-speed Ethernet (TSE) configurations that require an auto-negotiation sequency.
The insertion/deletion operation could break the auto-negotiation functionality due to the rate matching of different frequency PPM scenarios.The soft rate match FIFO is constructed in the GbE Serial Gigabit Media Independent Interface
(SGMII) IP core.
3. The byte serializer can be enabled or disabled.
4. The byte deserializer can be enabled or disabled.
8
8
125 MHz
125 MHz
Note: The transceivers do not have built-in support for other PCS functions; for example, the auto-
negotiation state machine, collision-detect, and carrier-sense. If required, you must implement
these functions in the FPGA fabric or external circuits.
GbE with IEEE 1588v2
GbE with IEEE 1588v2 provides a standard method to synchronize devices on a network with submicro‐
second precision. To improve performance, the protocol synchronizes slave clocks to a master clock so
that events and time stamps are synchronized in all devices. The protocol enables heterogeneous systems
that include clocks of various inherent precision, resolution, and stability to synchronize to a grandmaster
clock.
Related Information
Triple-Speed Ethernet MegaCore Function User Guide.
For more information about the IEEE 1588v2 implementation in GbE PHY and MAC, and design
examples.
UG-01143
2015.05.11
Gigabit Ethernet (GbE) and GbE with IEEE 1588v2
2-99
Implementing Protocols in Arria 10 Transceivers
Altera Corporation
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