User guide

Table 2-77: Block Sync Parameters
Parameter Value
Enable RX block synchronizer On
Enable rx_enh_blk_lock port On / Off
Table 2-78: Gearbox Parameters
Parameter Value
Enable TX data bitslip Off
Enable TX data polarity inversion On / Off
Enable RX data bitslip Off
Enable RX data polarity inversion On / Off
Enable tx_enh_bitslip port Off
Enable rx_bitslip port Off
Table 2-79: Dynamic Reconfiguration Parameters
Parameter Value
Enable dynamic reconfiguration On / Off
Share reconfiguration interface On / Off
Enable Altera Debug Master Endpoint On / Off
Enable capability registers On / Off
Set user-defined IP indentifier: 0 to 255
Enable control and status registers On / Off
Enable prbs soft accumulators On / Off
Table 2-80: Configuration Files Parameters
Parameter Value
Configuration file prefix —
2-96
Native PHY IP Parameter Settings for Interlaken
UG-01143
2015.05.11
Altera Corporation
Implementing Protocols in Arria 10 Transceivers
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