User guide

Table 2-71: Enhanced PCS Parameters
Parameter Value
Enhanced PCS / PMA interface width 32, 40, 64
FPGA fabric / Enhanced PCS interface
width
67
Enable 'Enhanced PCS' low latency
mode
Allowed when the PMA interface width is 32 and preset
variations for data rate is 10.3125 Gbps or 6.25 Gbps; otherwise
Off
Enable RX/TX FIFO double-width
mode
Off
TX FIFO mode Interlaken
TX FIFO partially full threshold 8 to 15
TX FIFO partially empty threshold 1 to 8
Enable tx_enh_fifo_full port On / Off
Enable tx_enh_fifo_pfull port On / Off
Enable tx_enh_fifo_empty port On / Off
Enable tx_enh_fifo_pempty port On / Off
RX FIFO mode Interlaken
RX FIFO partially full threshold from 10-29 (no less than pempty_threshold+8)
RX FIFO partially empty threshold 2 to 10
Enable RX FIFO alignment word
deletion (Interlaken)
On / Off
Enable RX FIFO control word deletion
(Interlaken)
On / Off
Enable rx_enh_data_valid port On / Off
Enable rx_enh_fifo_full port On / Off
Enable rx_enh_fifo_pfull port On / Off
Enable rx_enh_fifo_empty port On / Off
UG-01143
2015.05.11
Native PHY IP Parameter Settings for Interlaken
2-93
Implementing Protocols in Arria 10 Transceivers
Altera Corporation
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