User guide

• Resetting Transceiver Channels on page 4-1
Reset controller general information and implementation details
• Enhanced PCS Ports on page 2-54
For detailed information about the available ports in the Interlaken protocol.
Design Example
Altera provides a PHY layer-only design example to help you integrate an Interlaken PHY into your
complete design.
The TX soft bonding logic is included in the design example. Altera recommends that you integrate this
module into your design.
The Interlaken Design Example is available on the Arria 10 Transceiver PHY Design Examples Wiki page.
Note:
The design examples on the Wiki page provide useful guidance for developing your own designs,
but they are not guaranteed by Altera. Use them with caution.
Related Information
Interlaken Design Example
Native PHY IP Parameter Settings for Interlaken
Table 2-68: General and Datapath Parameters
Parameter Value
Message level for rule violations error
warning
Transceiver configuration rules Interlaken
PMA configuration rules basic
Transceiver mode TX / RX Duplex
TX Simplex
RX Simplex
Number of data channels 1 to 96
Data rate Up to 17.4 Gbps
(Depending on Enhanced PCS to PMA interface width
selection)
Enable datapath and interface reconfi‐
guration
On / Off
Enable simplified data interface On / Off
2-90
Design Example
UG-01143
2015.05.11
Altera Corporation
Implementing Protocols in Arria 10 Transceivers
Send Feedback