User guide

Figure 2-24: 24 Lanes Bonded Interlaken Link, TX Direction
To show more details, three different time segments are shown with the same zoom level.
24`h000000
24`h000000
24`... 24`hffffff
24`h000000
24`hffffff24`h000000
24`h000000
24`h00000024`hffffff
24`hffffff
24`hffffff 24`h000000
24`h000000
1536`h0123456789abcdef01234567
72`h249249249249249249
24`h000000
24`hffffff
24`...
24`h000000
24`h000000
24`hffffff
24`hffffff
24`h000000
24`h000...
24`h000000
24`h000000
24`h000000
1536`h0123456789abcdef01234567
72`h249249249249249249
24`h000000
24`h000000
24`h000000
24`hffffff
24`hffffff
24`hffffff
1536`h0123456789abcdef01234567
72`h249249249249249249
24`h000000
24`h000000
24`hffffff
24`h000000
24`h000000
24`h000000
24`h000000
1536`hbd212...
pll_locked
tx_analogreset
tx_clkout[0]
tx_clkout
tx_digitalreset
tx_ready[0]
tx_ready
tx_enh_data_valid[0]
tx_enh_data_valid
tx_enh_fifo_full
tx_enh_frame[0]
tx_enh_frame
tx_enh_frame_burst_en[0]
tx_enh_frame_burst_en
tx_parallel_data
tx_control
tx_enh_fifo_empty
tx_enh_fifo_pempty
tx_ready
Asserted
Pre-Fill
Stage
Pre-Fill Completed
Assert burst_en for
All Lanes
Send Data
Based on
FIFO Flags
Figure 2-25: 24 Lanes Bonded Interlaken Link, RX Direction
To show more details, three different time segments are shown with different zoom level.
rx_clkout[0]
rx_digitalreset
rx_ready
rx_enh_blk_lock
rx_enh_frame_lock
rx_enh_fifo_pfull[0]
rx_enh_fifo_pfull
rx_enh_fifo_pempty
rx_enh_fifo_align_clr
rx_enh_fifo_align_val
rx_enh_fifi_rd_en
rx_enh_data_valid
rx_parallel_data
rx_control
24`h00000024`hffffff
24`h000000
24`hffffff
24`h000000
24`h000000
24`h000000
24`h000000
24`h000000
24`h000000
24`h000000
1536`h0100009c0100
240`h0441104411044
24`hffffff
24`hffffff
24`h00000124`h0...
24`h000000
24`hffffff
24`h000000
24`h00...
24`h000000
24`h000000
1536`h0100009c0100009c0100009c0100009c0100009c0100009c0100009c01000
240`h044110441104404411044110441104411044110441104411044110441104411
24`hfffffe
24`h000001
24`h000000
24`hffffff
24`hffffff
24`h000000
24`hffffff
24`hffffff
24`hffffff
24`h000000
24`hffffff
24`h000000
24`hffffff
24`h00..
24`h000000
24`h000000
1536`h01000...
240`h044110...
24`h000000 24`h000000
24`hffffff 24`hffffff24`h00..
24`hffffff 24`hffffff
24`h00..
1536`h1e...
240`h90a... 240`h826...
rx_ready
Asserted
24`h00...
24`hff...
Some Lanes pfull Signal Is Asserted
before All Lanes pempty is Deasserted;
RX Deskew Fails. Need to Realign
Assert align_clr
to Re-Align
All Lanes pfull Low and All
Lanes pempty Deasserted
RX Deskew Complete
Start Reading Data
Based on FIFO Flags
24`h00..
Related Information
• Arria 10 Enhanced PCS Architecture on page 5-18
For more information about Enhanced PCS architecture
• Arria 10 PMA Architecture on page 5-1
For more information about PMA architecture
• Using PLLs and Clock Networks on page 3-49
For more information about implementing PLLs and clocks
• PLLs on page 3-3
PLL architecture and implementation details
UG-01143
2015.05.11
How to Implement Interlaken in Arria 10 Transceivers
2-89
Implementing Protocols in Arria 10 Transceivers
Altera Corporation
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