User guide

Interlaken operates on 64-bit data words and 3 control bits, which are striped round-robin across the
lanes. The protocol accepts packets on 256 logical channels and is expandable to accommodate up to
65,536 logical channels. Packets are split into small bursts that can optionally be interleaved. The burst
semantics include integrity checking and per logical channel flow control.
The Interlaken interface is supported with 1 to 48 lanes running at data rates up to 17.4 Gbps per lane on
Arria 10 devices. Interlaken is implemented using the Enhanced PCS. The Enhanced PCS has
demonstrated interoperability with Interlaken ASSP vendors and third-party IP suppliers.
Arria 10 devices provide three preset variations for Interlaken in the IP Parameter Editor:
• Interlaken 10x12.5 Gbps
• Interlaken 1x6.25 Gbps
• Interlaken 6x10.3 Gbps
Depending on the line rate, the enhanced PCS can use a PMA to PCS interface width of 32, 40, or 64 bits.
Figure 2-10: Transceiver Channel Datapath and Clocking for Interlaken
This figure assumes the serial data rate is 12.5 Gbps and the PMA width is 40 bits.
Transmitter Enhanced PCSTransmitter PMA
Receiver PMA
Receiver Enhanced PCS
TX
Gearbox
tx_serial_data
Serializer
Interlaken
Disparity Generator
Scrambler
PRBS
Generator
PRP
Generator
rx_serial_data
Deserializer
CDR
Descrambler
Interlaken
Disparity Checker
Block
Synchronizer
Interlaken
Frame Sync
RX
Gearbox
PRBS
Verifier
Transcode
Decoder
KR FEC RX
Gearbox
KR FEC
Decoder
KR FEC
Block Sync
KR FEC
Descrambler
Parallel Clock (312.5 MHz)
Parallel Clock (312.5 MHz)
Parallel Clock
Serial Clock
Parallel and Serial Clocks
Clock Divider
Parallel and Serial Clocks
Clock Generation Block (CGB)
Serial Clock
Serial Clock (6.25 GHz)
(6.25 GHz) =
Data rate/2
Input Reference Clock
64 bits
data +
3 bits
control
64 bits
data +
3 bits
control
ATX PLL
fPLL
CMU PLL
64B/66B Decoder
and RX SM
10GBASE-R
BER Checker
PRP
rx_pma_div_clkout
tx_pma_div_clkout
Verifier
rx_coreclkin
rx_clkout
186.57 MHz
to 312.5MHz
186.57 MHz
to 312.5MHz
Enhanced PCS
TX FIFO
Enhanced PCS
RX FIFO
Interlaken
Frame Generator
Interlaken
CRC32 Generator
Interlaken
CRC32 Checker
64B/66B Encoder
and TX SM
FPGA
Fabric
tx_coreclkin
tx_clkout
KR FEC
TX Gearbox
KR FEC
Scrambler
KR FEC
Encoder
Transcode
Encoder
Div 40
40
40
UG-01143
2015.05.11
Interlaken
2-77
Implementing Protocols in Arria 10 Transceivers
Altera Corporation
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