User guide
Table 2-67: Transceiver Native PHY Files and Directories
File Name Description
<project_dir> The top-level project directory.
<your_ip_name> .v or .vhd The top-level design file.
<your_ip_name> .qip A list of all files necessary for Quartus II compila‐
tion.
<your_ip_name> .bsf A Block Symbol File (.bsf) for your Transceiver
Native PHY instance.
<project_dir>/<your_ip_name>/ The directory that stores the HDL files that define
the Transceiver Native PHY IP.
<project_dir>/sim The simulation directory.
<project_dir>/sim/aldec Simulation files for Riviera-PRO simulation tools.
<project_dir>/sim/cadence Simulation files for Cadence simulation tools.
<project_dir>/sim/mentor Simulation files for Mentor simulation tools.
<project_dir>/sim/synopsys Simulation files for Synopsys simulation tools.
<project_dir>/synth The directory that stores files used for synthesis.
The Verilog and VHDL Transceiver Native PHY IP cores have been tested with the following simulators:
• ModelSim SE
• Synopsys VCS MX
• Cadence NCSim
If you select VHDL for your transceiver PHY, only the wrapper generated by the Quartus II software is in
VHDL. All the underlying files are written in Verilog or SystemVerilog. To enable simulation using a
VHDL-only ModelSim license, the underlying Verilog and SystemVerilog files for the Transceiver Native
PHY IP are encrypted so that they can be used with the top-level VHDL wrapper without using a mixed-
language simulator.
For more information about simulating with ModelSim, refer to the Mentor Graphics ModelSim Support
chapter in volume 3 of the Quartus II Handbook.
The Transceiver Native PHY IP cores do not support the NativeLink feature in the Quartus II software.
Related Information
• Simulating the Transceiver Native PHY IP Core on page 2-322
• Mentor Graphics ModelSim Support
Interlaken
Interlaken is a scalable, channelized chip-to-chip interconnect protocol.
The key advantages of Interlaken are scalability and low I/O count compared to earlier protocols such as
SPI 4.2. Other key features include flow control, low overhead framing, and extensive integrity checking.
2-76
Interlaken
UG-01143
2015.05.11
Altera Corporation
Implementing Protocols in Arria 10 Transceivers
Send Feedback