User guide

IP Core File Locations
When you generate your Transceiver Native PHY IP, the Quartus
®
II software generates the HDL files
that define your instance of the IP. In addition, the Quartus II software generates an example Tcl script to
compile and simulate your design in the ModelSim simulator. It also generates simulation scripts for
Synopsys VCS, Aldec Active-HDL, Aldec Riviera-Pro, and Cadence Incisive Enterprise.
Figure 2-9: Directory Structure for Generated Files
<Project Directory>
<your_ip_or_system_name>.qsys - Top-level IP variation file
<your_ip_or_system_name>.sopcinfo
<your_ip_name> - IP core variation files
<your_ip_name>.cmp - VHDL component declaration file
<your_ip_name>_bb - Verilog HDL black-box EDA synthesis file
<your_ip_name>_inst - IP instantiation template file
<your_ip_name>.ppf - XML I/O pin information file
<your_ip_name>.qip - Lists IP synthesis files
<your_ip_name>.sip - Lists files for simulation
<your_ip_name>.v or .vhd - Greybox timing netlist
synth - IP synthesis files
<your_ip_name>.v or .vhd - Top-level IP synthesis file
sim - IP simulation files
<your_ip_name>.v or .vhd - Top-level simulation file
aldec- Simulator setup scripts
<IP subcore> - IP subcore files
<HDL files>
sim
cadence - Simulator setup scripts
mentor - Simulator setup scripts
synopsys - Simulator setup scripts
<HDL files>
synth
The following table describes the directories and the most important files for the parameterized
Transceiver Native PHY IP core and the simulation environment. These files are in clear text.
UG-01143
2015.05.11
IP Core File Locations
2-75
Implementing Protocols in Arria 10 Transceivers
Altera Corporation
Send Feedback