User guide

Name Direction Clock Domain Description
tx_std_bitslipboun-
darysel[5 <n>-1:0]
Input
Asynchronous Bitslip boundary selection signal. Specifies the
number of bits that the TX bit slipper must slip.
rx_std_bitslipboun-
darysel[5 <n>-1:0]
Output
Asynchronous This port is used in deterministic latency word
aligner mode. It reports the number of bits that the
RX block slipped to achieve deterministic latency.
rx_std_wa_patterna-
lign[<n>-1:0]
Input
Asynchronous Active when you place the word aligner in manual
mode. In manual mode, you align words by
asserting rx_std_wa_patternalign. When the
PCS-PMA Interface width is 10 bits, rx_std_wa_
patternalign is level sensitive. For all the other
PCS-PMA Interface widths, rx_std_wa_patterna-
lign is positive edge sensitive.
You can use this port only when the word aligner is
configured in manual or deterministic latency
mode.
When the word aligner is in manual mode, and the
PCS-PMA interface width is 10 bits, this is a level
sensitive signal. In this case, the word aligner
monitors the input data for the word alignment
pattern, and updates the word boundary when it
finds the alignment pattern.
For all other PCS-PMA interface widths, this signal
is edge sensitive.This signal is internally synchron‐
ized inside the PCS using the PCS parallel clock and
should be asserted for at least 2 clock cycles to allow
synchronization.
rx_std_wa_
a1a2size[<n>-1:0]
Input
Asynchronous Used for the SONET protocol. Assert when the A1
and A2 framing bytes must be detected. A1 and A2
are SONET backplane bytes and are only used when
the PMA data width is 8 bits.
rx_bitslip[<n>-1:0] Input
Asynchronous Used when word aligner mode is bitslip mode.
When the Word Aligner is in either Manual (PLD
controlled), Synchronous State Machine or
Deterministic Latency ,the rx_bitslip signal is
not valid and should be tied to 0. For every rising
edge of the rx_std_bitslip signal, the word
boundary is shifted by 1 bit. Each bitslip removes
the earliest received bit from the received data.
UG-01143
2015.05.11
Standard PCS Ports
2-73
Implementing Protocols in Arria 10 Transceivers
Altera Corporation
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