User guide

Name Direction Clock Domain Description
unused_tx_
parallel_data
Input
tx_clkout This signal specifies the unused data when you turn
on Enable simplified data interface. When
simplified data interface is not set, the unused bits
are a part of tx_parallel_data. Connect all these
bits to 0. If you do not connect the unused data bits
to 0, then TX parallel data may not be serialized
correctly by the Native PHY IP core.
tx_coreclkin Input Clock
The FPGA fabric clock. This clock drives the write
port of the TX FIFO.
tx_clkout
Output
Clock
This is the parallel clock generated by the local CGB
for non bonded configurations, and master CGB for
bonded configuration. This clocks the tx_
parallel_data from the FPGA fabric to the TX
PCS.
Table 2-61: RX Standard PCS: Data, Control, Status, and Clocks
Name Direction Clock Domain Description
rx_parallel_
data[<n> 128-1:0]
Output Synchronous
to the clock
driving the
read side of
the FIFO
(rx_
coreclkin
or rx_
clkout)
RX parallel data from the RX PCS to the FPGA
fabric. For each 128-bit word of rx_parallel_data,
the data bits correspond to rx_parallel_data[7:0]
when 8B/10B decoder is enabled and rx_parallel_
data[9:0] when 8B/10B decoder is disabled.
unused_rx_
parallel_data
Output Synchronous
to the clock
driving the
read side of
the FIFO
(rx_
coreclkin
or rx_
clkout)
This signal specifies the unused data when you turn
on Enable simplified data interface. When
simplified data interface is not set, the unused bits
are a part of rx_parallel_data. These outputs can
be left floating.
rx_clkout
Output
Clock
The low speed parallel clock recovered by the
transceiver RX PMA, that clocks the blocks in the RX
Standard PCS.
UG-01143
2015.05.11
Standard PCS Ports
2-69
Implementing Protocols in Arria 10 Transceivers
Altera Corporation
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