User guide

Chapter 6: PHY IP Core for PCI Express (PIPE) 6–17
Interfaces
March 2012 Altera Corporation Altera Transceiver PHY IP Core
User Guide
Dynamic Reconfiguration
As silicon progresses towards smaller process nodes, circuit performance is affected
more by variations due to process, voltage, and temperature (PVT). These process
variations result in voltages that can be offset from required ranges. The calibration
performed by the dynamic reconfiguration interface compensates for variations due
to PVT.
0x085
[31:4] RW Reserved —
[3] RW
rx_bitslip
When set, the word alignment logic operates in bitslip
mode. Every time this register transitions from 0 to 1, the
RX data slips a single bit.
To block: Word aligner.
[2] RW
rx_bytereversal_enable
When set, enables byte reversal on the RX interface.
To block: Word aligner.
[1] RW
rx_bitreversal_enable
When set, enables bit reversal on the RX interface.
To block: Word aligner.
[0] RW
rx_enapatternalign
When set, the word alignment logic operates in pattern
detect mode.
To block: Word aligner.
0x086
[31:20] R Reserved —
[19:16] R
rx_rlv
When set, indicates a run length violation.
From block: Word aligner.
[15:12] R
rx_patterndetect
When set, indicates that RX word aligner has achieved
synchronization.
From block: Word aligner.
[11:8] R
rx_disperr
When set, indicates that the received 10-bit code or data
group has a disparity error. When set, the corresponding
errdetect bits are also set.
From block: 8B/10B decoder.
[7:4] R
rx_syncstatus
When set, indicates that the RX interface is synchronized
to the incoming data.
From block: Word aligner.
[3:0] R
rx_errdetect
When set, indicates that a received 10-bit code group has
an 8B/10B code violation or disparity error. It is used
along with RX disparity to differentiate between a code
violation error and a disparity error, or both.
In PIPE mode, the PIPE specific output port called
pipe_rxstatus encodes the errors.
From block: 8B/10B decoder.
Table 6–12. PCI Express PHY (PIPE) IP Core Registers (Part 4 of 4)
Word
Addr
Bits R/W Register Name Description