User guide

6–16 Chapter 6: PHY IP Core for PCI Express (PIPE)
Interfaces
Altera Transceiver PHY IP Core March 2012 Altera Corporation
User Guide
0x066 [31:0] R pma_rx_is_lockedtodata
When asserted, indicates that the RX CDR PLL is locked
to the RX data, and that the RX CDR has changed from
LTR to LTD mode. Bit <n> corresponds to channel <n>.
00x067 [31:0] R
pma_rx_is_lockedtoref
When asserted, indicates that the RX CDR PLL is locked
to the reference clock. Bit <n> corresponds to channel
<n>.
PCS for PCI Express
0x080 [31:0] RW
Lane or group number
Specifies lane or group number for indirect addressing,
which is used for all PCS control and status registers. For
variants that stripe data across multiple lanes, this is the
logical group number. For non-bonded applications, this
is the logical lane number.
0x081
[31:6] R Reserved —
[5:1] R
rx_bitslipboundary
selectout
Records the number of bits slipped by the RX Word
Aligner to achieve word alignment. Used for very latency
sensitive protocols.
From block: Word aligner.
[0] R
rx_phase_comp_fifo_error
When set, indicates an RX phase compensation FIFO
error.
From block: RX phase compensation FIFO.
0x082
[31:1] R Reserved —
[0] RW
tx_phase_comp_fifo_error
When set, indicates a TX phase compensation FIFO error.
From block: TX phase compensation FIFO.
0x083
[31:6] RW Reserved —
[5:1] RW
tx_bitslipboundary_select
Records the number of bits slipped by the TX bit slipper in
the TX serial output. Used for very latency sensitive
protocols.
From block: TX bit-slipper.
[0] RW
tx_invpolarity
When set, the TX channel inverts the polarity of the TX
data.
To block: Serializer.
0x084
[31:1] RW Reserved —
[0] RW
rx_invpolarity
When set, the RX channel inverts the polarity of the
received data. The 8B/10B decoder inverts the decoder
input sample and then decodes the inverted samples.
To block: 8B/10B decoder.
Table 6–12. PCI Express PHY (PIPE) IP Core Registers (Part 3 of 4)
Word
Addr
Bits R/W Register Name Description