User guide

Chapter 6: PHY IP Core for PCI Express (PIPE) 6–13
Interfaces
March 2012 Altera Corporation Altera Transceiver PHY IP Core
User Guide
Registers
The Avalon-MM PHY management interface provides access to the PHY IP Core for
PCI Express PCS and PMA features that are not part of the standard PIPE interface.
You can use an embedded controller acting as an Avalon-MM master to send read and
write commands to this Avalon-MM slave interface.
Figure 6–4 provides a high-level view of this hardware.
rx_syncstatus[<d><n>/8-1:0] Output
Indicates presence or absence of synchronization on the RX interface.
Asserted when word aligner identifies the word alignment pattern or
synchronization code groups in the received data stream.
rx_signaldetect[<d><n>/8-
1:0]
Output
When asserted indicates that the lane detects a sender at the other
end of the link.
Note to Table 6–10:
(1) <n> is the number of lanes. <d> is the deserialization factor. <p> is the number of PLLs.
Table 6–10. Status Signals (Part 2 of 2)
(1)
Signal Name Direction Signal Name
Figure 6–4. PCI Express PIPE IP Core
(1)
Note to Figure6–4:
(1) Blocks in gray are soft logic. Blocks in white are hard logic.
System
Interconnect
Fabric
System
Interconnect
Fabric
to
Reconfiguration
Controller
Clocks
Tx Data, Datak
PIPE Control
PHY IP Core for PCI Express
Hard PCS and PMA
PHY IP Core for PCI Express and Avalon-MM Control Interface for Non-PIPE Functionality
Dynamic
Reconfiguration
PIPE Control
Tx Data, Datak
Clocks
PIPE Status
Rx Data, Datak
Valid
Clocks
Reset
Non-PIPE
Status
Non-PIPE
Control
S
Avalon-MM
Control
Non-PIPE
S
Avalon-MM
Status
Non-PIPE
Reset
Controller
PIPE reset
M
Avalon-MM
PHY
Mgmt
S