User guide

Chapter 6: PHY IP Core for PCI Express (PIPE) 6–9
Interfaces
March 2012 Altera Corporation Altera Transceiver PHY IP Core
User Guide
1 The block diagram shown in the GUI labels the external pins with the interface type
and places the interface name inside the box. The interface type and name are used in
the _hw.tcl file. If you turn on Show signals, the block diagram displays all top-level
signal names.
f For more information about _hw.tcl files, refer to refer to the Component Interface Tcl
Reference chapter in volume 1 of the Quartus II Handbook.
The following sections describe the signals in each interface.
Avalon-ST TX Input Data from the PHYMAC
Table 6–6 describes the signals in the Avalon-ST input interface. These signals are
driven from the PHYMAC to the PCS. This is an Avalon sink interface.
f For more information about the Avalon-ST protocol, including timing diagrams, refer
to the Avalon Interface Specifications.
Avalon-ST RX Output Data to the PHYMAC
Table 6–7 describes the signals in the Avalon-ST output interface. These signals are
driven from the PHY to the PHYMAC. This is an Avalon source interface.
Table 6–6. Avalon-ST TX Inputs
Signal Name Dir Description
pipe_txdata[<n><d>-1:0] Sink
This is TX parallel data driven from the PHYMAC for PCI Express. The
ready latency on this interface is 0, so that the PHY must be able to
accept data as soon as the PHY exits reset.
pipe_txdatak[<n><d>/8-1:0] Sink
Data and control indicator for the received data. When 0, indicates that
pipe_txdata is data, when 1, indicates that pipe_txdata is control.
Table 6–7. Avalon-ST RX Inputs
Signal Name Dir Description
pipe_rxdata[<n><d>-1:0] Source
This is RX parallel data driven from the PHY. The ready latency on this
interface is 0, so that the MAC must be able to accept data as soon as the
PHY comes out of reset.
pipe_rxdatak[<n><d>/8-1:0] Source
Data and control indicator for the source data. Bit 0 correspond the low
byte of
pipe_rxdata . Bit 1 corresponds to the upper byte. When 0,
indicates that
pipe_rxdata is data, when 1, indicates that
pipe_rxdata is control.
pipe_rxvalid[<n>-1:0] Source Asserted when RX data and control are valid.