User guide

6–8 Chapter 6: PHY IP Core for PCI Express (PIPE)
Interfaces
Altera Transceiver PHY IP Core March 2012 Altera Corporation
User Guide
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Interfaces
This section describes interfaces of the PHY IP Core for PCI Express (PIPE). It includes
the following topics:
■ Ports
■ Registers
■ Dynamic Reconfiguration
Ports
Figure 6–2 illustrates the top-level pinout of the PHY IP core for PCI Express PHY.
Figure 6–2. Top-Level Signals of the PHY IP Core for PCI Express
(1)
Note to Figure6–2:
(1) < n > is the number of lanes. <d> is the total deserialization factor from the input pin to the PHYMAC interface. <s> is the symbols size.<r> is the
width of the reconfiguration interface; <r> is automatically calculated based on the selected configuration.
pipe_txdata[<n><d>-1:0]
pipetx_datak[<n><d>/8-1:0]
pipe_rxdata[<n><d>-1:0]
pipe_rxdatak[<n><d>/8-1:0]
pipe_rxvalid[<n>-1:0]
phy_mgmt_clk
phy_mgmt_clk_reset
phy_mgmt_address[8:0]
phy_mgmt_writedata[31:0]
phy_mgmt_readdata[31:0]
phy_mgmt_write
phy_mgmt_read
phy_mgmt_waitrequest
pll_ref_clk
fixedclk
pipe_pclk
pipe_txdetectrx_loopback[<n>-1:0]
pipe_txelecidle[<n>-1:0]
pipe_txdeemph[<n>-1:0]
pipe_txcompliance[<n>-1:0]
pipe_txmargin[3<n>-1:0]
pipe_rate[1:0]
pipe_powerdown[2<n>-1:0]
pipe_rxpolarity[<n>-1:0]
pipe_rxelecidle[<n>-1:0]
pipe_phystatus[<n>-1:0]
pipe_rxstatus[3<n>-1:0]
rx_eidleinfersel
pipe_txswing[<n>-1:0]
PHY IP Core for PCI Express Top-Level Signals
tx_serial_data[<n>-1:0]
rx_serial_data[<n>-1:0]
rx_ready
rx_ready
pll_locked
rx_is_lockedtodata[<n>-1:0]
rx_is_lockedtoref[<n>-1:0]
rx_syncstatus[<d>/<n><s>-1:0]
rx_signaldetect[<d>/<n><s>-1:0]
Avalon-ST Tx
from PCI Express
PHYMAC
High Speed
Serial I/O
Avalon-MM PHY
Management
Interface
Avalon-ST Rx
to PCI Express
PHYMAC
Pipe Interface
Avalon-ST Sink
and Source
Status
reconfig_to_xcvr[(<r>70)-1:0]
reconfig_from_xcvr[(<r>46)-1:0]
Dynamic
Reconfiguatio
n