User guide

Chapter 5: Interlaken PHY IP Core 5–9
Interfaces
March 2012 Altera Corporation Altera Transceiver PHY IP Core
User Guide
f For more information about _hw.tcl, files refer to the Component Interface Tcl Reference
chapter in volume 1 of the Quartus II Handbook.
The following sections describe the signals in each interface.
Avalon-ST TX Interface
Table 5–6 lists the signals in the Avalon-ST TX interface.
Table 5–6. Avalon-ST TX Signals
Signal Name Direction Description
tx_parallel_data<n>[63:0] Sink Avalon-ST data bus driven from the FPGA fabric to the TX PCS.
tx_parallel_data<n>[64] Sink
Indicates whether
tx_parallel_data<n>[63:0] represents control
or data. When deasserted,
tx_parallel_data<n>[63:0] is a data
word. When asserted,
tx_parallel_data<n>[63:0] is a control
word.
The value of header synchronization bits[65:64] of the Interlaken word
identify whether bits[63:0] are a Framing Layer Control/Burst/IDLE
Control Word or a data word. The MAC must gray encode the header
synchronization bits. The value 2’b10 indicating Burst/IDLE Control
Word must be gray encoded to the value 1’b1 for
tx_parallel_data<n>[64] . The value 2’b01 indicating data word
must be gray encoded to the value 1’b0 for
tx_parallel_data<n>[64] .
tx_parallel_data<n>[65] Sink
When asserted, indicates that
tx_parallel_data<n>[63:0] is valid
and is ready to be written into the TX FIFO. When deasserted, indicates
that
tx_parallel_data<n>[63:0] is invalid and is not written into
the TX FIFO.
The Interlaken MAC should gate
tx_parallel_data<n>[65] based
on
tx_datain_bp<n> .
tx_ready Source
When asserted, indicates that the TX interface has exited the reset
state and is ready for service. The
tx_ready latency for the TX
interface is 0. A 0 latency means that the TX FIFO can accept data on
the same clock cycle that
tx_ready is asserted if
tx_parallel_data[65] (valid) is also asserted. The Interlaken MAC
must wait for
tx_parallel_data[65] before initiating data transfer
on any lanes. The TX FIFO only captures input data from the Interlaken
MAC when
tx_ready and tx_parallel_data[65] are both
asserted.
For more information about the Avalon-ST interface and the use of
ready signals, refer to the “Data Transfer with Backpressure” section in
the “Avalon Streaming Interfaces” chapter of the Avalon Interface
Specifications .
tx_datain_bp<n> Source
When asserted, indicates that Interlaken TX lane <n> interface is ready
to receive data for transmission. The latency on this Avalon-ST
interface is 0 cycles. The Interlaken MAC should drive
tx_parallel_data<n>[63:0] as soon as tx_ready<n> and
tx_sync_done are asserted. The tx_datain_bp<n> signal is
connected to the
~partialfull of the TX FIFO, so that when
tx_datain_bp<n> is deasserted the TX FIFO is almost full and back
pressures the Interlaken MAC.