User guide

5–8 Chapter 5: Interlaken PHY IP Core
Interfaces
Altera Transceiver PHY IP Core March 2012 Altera Corporation
User Guide
h For more information about the Pin Planner, refer to About the Pin Planner in
Quartus II Help. For more information about the Assignment Editor, refer to About
the Assignment Editor in Quartus II Help.
f For more information about Quartus II Settings, refer to Quartus II Settings File
Manual.
Interfaces
This section describes interfaces of the Interlaken Transceiver PHY. It includes the
following sections:
■ Ports
■ Registers
■ Transceiver Reconfiguration
Ports
Figure 5–2 illustrates the top-level signals of the Interlaken PHY IP core.
1 The block diagram shown in the GUI labels the external pins with the interface type
and places the interface name inside the box. The interface type and name are used to
define interfaces in the _hw.tcl. writing
Figure 5–2. Top-Level Interlaken PHY Signals
(1)
Note to Figure5–2:
(1) < n > = the number of channels in the interface, so that the width of tx_data in 4-channel instantiation is [263:0].
tx_parallel_data<n>[65:0]
tx_ready
tx_datain_bp<n>
tx_clkout<n>
tx_user_clkout
pll_locked
tx_sync_done
rx_parallel_data<n>[71:0]
rx_ready
rx_clkout<n>
rx_fifo_clr<n>
rx_dataout_bp<n>
phy_mgmt_clk
phy_mgmt_clk_reset
phy_mgmt_address[8:0]
phy_mgmt_writedata[31:0]
phy_mgmt_readdata[31:0]
phy_mgmt_write
phy_mgmt_read
phy_mgmt_waitrequest
pll_ref_clk
Interlaken Top-Level Signals
tx_serial_data<n>
rx_serial_data<n>
Avalon-ST
TX to/ from
MAC
High Speed
Serial I/O
PLL
Avalon-MM PHY
Management
Interface
Avalon-ST
RX from/to
MAC
Dynamic
Reconfiguatio
n
tx_coreclkin
rx_coreclkin
reconfig_to_xcvr[(<n>70-1):0]
reconfig_from_xcvr[(<n>46-1):0]
FIFO Clock
Input
(Optional)