User guide

Chapter 5: Interlaken PHY IP Core 5–3
Parameter Settings
March 2012 Altera Corporation Altera Transceiver PHY IP Core
User Guide
Advanced Options
Table 5–2 describes the parameters that you can set on the Optional Ports tab.
Input clock frequency
Lane rate/<n>
Lane rate/80
Lane rate/64
Lane rate/50
Lane rate/40
Lane rate/32
Lane rate/25
Lane rate/20
Lane rate/16
Lane rate/12.5
Lane rate/10
Lane rate/8
Specifies the frequency of the input reference clock. The default
value for the Input clock frequency is the Lane rate /20; however,
you can change this value. Many reference clock frequencies are
available.
PLL type
CMU
ATX
Specifies the PLL type.
The CMU PLL has a larger frequency range than the ATX PLL. The
ATX PLL is designed to improve jitter performance and achieves
lower channel-to-channel skew; however, it supports a narrower
range of data rates and reference clock frequencies. Another
advantage of the ATX PLL is that it does not use a transceiver
channel, while the CMU PLL does. Because the CMU PLL is more
versatile, it is specified as the default setting.
Base data rate
1 × Lane rate
2 × Lane rate
4 × Lane rate
This option allows you to specify a Base data rate to minimize the
number of PLLs required to generate the clocks necessary for
data transmission at different frequencies. Depending on the Lane
rate you specify, the default Base data rate can be either 1, 2, or 4
times the Lane rate; however, you can change this value. The
default value specified is for backwards compatibility with earlier
Quartus II software releases.
Table 5–2. General Option (Part 2 of 2)
Parameter Value Description
Table 5–3. Optional Ports
Parameter Value Description
Enable RX status
signals, (word lock,
sync lock, crc32
error) as part of
rx_parallel_data
On/Off
When you turn this option on,
rx_parallel_data[71:69] are
included in the top-level module. These optional signals report the
status of word and synchronization locks and CRC32 errors. Refer
to Table 5–7 on page 5–10 for more information. facilitate
Create tx_coreclkin
port
On/Off
The
tx_coreclkin drives the write side of TX FIFO. This clock is
required for lane synchronization.
tx_coreclkin must be used
when the number of lanes is greater than 1.
Create rx_coreclkin
port
On/Off
When selected
rx_coreclkin is available as input port which
drives the read side of RX FIFO, When deselected
rx_user_clkout, which is the master rx_clockout for all
bonded receiver lanes, is routed internally to drive the RX read
side of FIFO.
rx_user_clkout is also available as an output port
for the Interlaken MAC.