User guide

4–14 Chapter 4: XAUI PHY IP Core
Interfaces
Altera Transceiver PHY IP Core March 2012 Altera Corporation
User Guide
Table 4–9 describes the signals in the SDR TX XGMII interface.
SDR XGMII RX Interface
Table 4–10 describes the signals in the SDR RX XGMII interface.
Transceiver Serial Data Interface
Table 4–11 describes the signals in the XAUI transceiver serial data interface. There are
four lanes of serial data for both the TX and RX interfaces. This interface runs at
3.125 GHz or 6.25 GHz depending on the variant you choose. There is no separate
clock signal because it is encoded in the data.
Table 4–9. SDR TX XGMII Interface
Signal Name Direction Description
xgmii_tx_dc[71:0] Source
Contains 4 lanes of data and control for XGMII. Each lane consists of
16 bits of data and 2 bits of control.
■ Lane 0–[7:0]/[8], [43:36]/[44]
■ Lane 1–[16:9]/[17], [52:45]/[53]]
■ Lane 2–[25:18]/[26], [61:54]/[62]
■ Lane 3–[34:27]/[35],[70:63]/[71]
xgmii_tx_clk Input
The XGMII SDR TX clock which runs at 156.25 MHz or 312.5 for the
DDR variant.
Table 4–10. SDR RX XGMII Interface
Signal Name Direction Description
xgmii_rx_dc[71:0] Sink
Contains 4 lanes of data and control for XGMII. Each lane consists of
16 bits of data and 2 bits of control.
■ Lane 0–[7:0]/[8], [43:36]/[44]
■ Lane 1–[16:9]/[17], [52:45]/[53]]
■ Lane 2–[25:18]/[26], [61:54]/[62]
■ Lane 3–[34:27]/[35],[70:63]/[71]
xgmii_rx_clk Output The XGMII SDR RX MAC interface clock which runs at 156.25 MHz.
Table 4–11. Serial Data Interface
Signal Name Direction Description
xaui_rx_serial_data[3:0] Input Serial input data.
xaui_tx_serial_data[3:0] Output Serial output data.