User guide

4–10 Chapter 4: XAUI PHY IP Core
Configurations
Altera Transceiver PHY IP Core March 2012 Altera Corporation
User Guide
Configurations
Figure 4–2 illustrates one configuration of the XAUI IP core. As this figure illustrates,
if your variant includes a single instantiation of the XAUI IP core, the transceiver
reconfiguration control logic is included in the XAUI PHY IP core. For Stratix V
devices the Transceiver Reconfiguration Controller must always be external. Refer to
Chapter 10, Transceiver Reconfiguration Controller for more information about this IP
core.
Interfaces
This section describes interfaces of the XAUI PHY IP Core. It includes the following
topics:
■ Ports
■ Registers
■ Dynamic Reconfiguration
Figure 4–2. XAUI PHY with Internal Transceiver Reconfiguration Control
System
Interconnect
Fabric
System
Interconnect
Fabric
Inter-
leave
PCS
S
Alt_PMA
S
S
Low Latency
Controller
S
Transceiver
Reconfiguration
Controller
Transceiver Channel
Hard XAUI PHY
4 x 3.125 Gbps serial
4
4
To MAC
SDR XGMII
72 bits @ 156.25 Mbps
M
Avalon-MM
PHY
Mgmt
S
PMA Channel
Controller