User guide

Chapter 4: XAUI PHY IP Core 4–9
Parameter Settings
March 2012 Altera Corporation Altera Transceiver PHY IP Core
User Guide
h For more information about the Pin Planner, refer to About the Pin Planner in
Quartus II Help. For more information about the Assignment Editor, refer to About
the Assignment Editor in Quartus II Help.
f For more information about Quartus II Settings, refer to Quartus II Settings File
Manual.
Advanced Options
Table 4–8 describes the settings available on the Advanced Options tab.
XCVR_TX_VOD
Transmitter Differential
Output Voltage
Differential output voltage setting. The
values are monotonically increasing
with the driver main tap current
strength.
0–63
50
Pin
XCVR_TX_VOD_PRE_EMP_
CTRL_SRC
Transmitter V
OD
/
Preemphasis Control
Source
When set to
DYNAMIC_CTL , the PCS
block controls the V
OD
and
preemphasis coefficients for PCI
Express. When this assignment is set
to
RAM_CTL the V
OD
and preemphasis
are controlled by other assignments,
such as
XCVR_TX_PRE_EMP_1ST_POST_TAP .
DYNAMIC_CTL
RAM_CTL
Pin
Table 4–7. Transceiver and PLL Assignments for Stratix V Devices (Sheet 1 of 3)
QSF Assignment Name
Pin Planner and
Assignment Editor
Name
Description Options Assign To
Table 4–8. Advanced Options
Name Value Description
Include control and status portsOn/Off
If you turn this option on, the top-level IP core include the status
signals and digital resets shown in Figure 4–4 on page 4–12 and
Figure 4–3 on page 4–11. If you turn this option off, you can access
control and status information using Avalon-MM interface to the
control and status registers. The default setting is off.
External PMA control and
configuration
On/Off
If you turn this option on, the PMA signals are brought up to the top
level of the XAUI IP core. This option is useful if your design
includes multiple instantiations of the XAUI PHY IP core. To save
FPGA resources, you can instantiate the Low Latency PHY Controller
and Transceiver Reconfiguration Controller IP cores separately in
your design to avoid having these IP cores instantiated in each
instance of the XAUI PHY IP core. If you turn this option off, the
PMA signals remain internal to the core. The default setting is off.
This option is available for Arria II GX, HardCopy IV and Stratix IV
devices.
Enable rx_recovered_clk pin On/Off
When you turn this option on, the RX recovered clock signal is an
output signal.