User guide

March 2012 Altera Corporation Altera Transceiver PHY IP Core
User Guide
4. XAUI PHY IP Core
The Altera XAUI PHY IP core implements the IEEE 802.3 Clause 48 specification to
extend the operational distance of the XGMII interface and reduce the number of
interface signals. XAUI extends the physical separation possible between the 10 Gbps
Ethernet MAC function implemented in an Altera FPGA and the Ethernet standard
PHY component on a PCB to one meter. The XAUI IP core accepts 72-bit data (single
data rate–SDR XGMII) from the application layer at either 156.25 Mbps or 312.5 Mbps.
The serial interface runs at either 4 × 3.125 Gbps or 4 × 6.25 Gbps (DDR XAUI option).
Figure 4–1 illustrates the top-level blocks of the XAUI PHY IP core.
For Stratix IV GX and GT devices, you can choose a hard XAUI physical coding
sublayer (PCS) and physical media attachment (PMA), or a soft XAUI PCS and PMA
in low latency mode. You can also combine both hard and soft PCS configurations in
the same device, using all channels in a transceiver bank. The PCS is only available in
soft logic for Stratix V devices.
f For more detailed information about the XAUI transceiver channel datapath,
clocking, and channel placement, refer to the “XAUI” section in the Transceiver
Protocol Configurations in Stratix V Devices chapter of the Stratix V Device Handbook.
Figure 4–1. XAUI PHY IP Core
Note to Figure4–1:
(1) Refer to Table 4–2 on page 4–2 for a list of supported devices.
XAUI IP Core
4 x 3.125 Gbps serial
or
4 x 6.5 Gbps serial
Altera FPGA
Hard PMA
PCS
8B/10B
Word Aligner
Phase Comp
SDR XGMII
72 bits @ 156.25 Mbps
or
72 bits @ 312.5 Mbps
Avalon-MM
Control & Status
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