User guide

Additional InformationAdditional Information Info–7
Revision History
March 2012 Altera Corporation Altera Transceiver PHY IP Core
User Guide
Custom PHY Transceiver
May 2011 1.2
■ Added presets for the 3.25GbE and 1.25GbE protocols.
■ Moved dynamic reconfiguration for the transceiver outside of the Custom PHY IP Core. The
reconfiguration signals now connect to a separate Reconfiguration Controller IP Core.
■ Removed device support for Arria II GX, Arria II GZ, HardCopy IV GX, and Stratix IV GX.
■ Added the following parameters on the General tab:
■ Transceiver protocol
■ Create rx_recovered_clk port
■ Force manual reset control
■ Added optional rx_rmfifoddatainserted , rx_rmfifodatadelted , rx_rlv , and
rx_recovered_clk
as output signals.
■ Added phy_mgmt_waitrequest to the PHY management interface.
■ Renamed reconfig_fromgxb and reconfig_togxb reconfig_from_xcvr and
reconfig_to_xcvr , respectively.
■ Corrected address for 8-Gbps RX PCS status register in Table 7–21 on page 7–21.
■ Added special pad requirement for Byte ordering pattern. Refer to Table 7–7 on page 7–7.
■ Clarified behavior of the word alignment mode. Added note explaining how to disable all
word alignment functionality.
Low Latency PHY Transceiver
May 2011 1.2
■ Moved dynamic reconfiguration for the transceiver outside of the Low Latency PHY IP Core.
The reconfiguration signals now connect to a separate Reconfiguration Controller IP Core.
■ Moved dynamics reconfiguration for the transceiver outside of the Custom PHY IP Core. The
reconfiguration signals now connect to a separate Reconfiguration Controller IP Core.
■ Renamed the tx_parallel_clk signal tx_clkout .
Transceiver Reconfiguration Controller
May 2011 1.2
■ Added Stratix V support. The Transceiver Reconfiguration Controller is only available for
Stratix IV devices in the Transceiver Toolkit.
■ Added sections describing the number of reconfiguration interfaces required and
restrictions on channel placement.
■ Added pre- and post-serial loopback controls.
■ Changed reconfiguration clock source. In 10.1, the Avalon-MM PHY Management clock was
used for reconfiguration. In 11.0, the reconfiguration controller supplies this clock.
Migrating from Stratix IV to Stratix V
May 2011 1.2
■ Added discussion of dynamic reconfiguration for Stratix IV and Stratix V devices.
■ Added information on loopback modes for Stratix IV and Stratix V devices.
■ Added new parameters for Custom PHY IP core in Stratix V devices.
Date Version Changes Made SPR