User guide

Additional InformationAdditional Information Info–5
Revision History
March 2012 Altera Corporation Altera Transceiver PHY IP Core
User Guide
All Chapters
July 2011 1.2.1
■ Restricted frequency range of the phy_mgmt_clk to 90–100 MHz for the Transceiver
Reconfiguration Controller IP Core chapter. There is no restriction on the frequency of
phy_mgmt_clk for Stratix V devices in the 10GBASE-R, XAUI, Interlaken, PHY IP Core for
PCI Express, Custom, and Low Latency PHYs; however, to use the same clock source for
both, you must restrict this clock to 90–100 MHz.
■ Added column specifying availability of read and write access for PMA analog controls in the
Transceiver Reconfiguration Controller IP Core chapter.
■ Renamed Avalon-MM bus in for Transceiver Reconfiguration Controller reconfig_mgmt *.
■ Provided frequency range for phy_mgmt_clk for the XAUI PHY IP Core in Arria II GX,
Cyclone IV GX, HardCopy IV, and Stratix IV GX devices.
■ Added register descriptions for the automatic reset controller to the Low Latency PHY IP
Core chapter.
■ Added two steps to procedure to reconfigure a PMA control in the Transceiver
Reconfiguration Controller chapter.
■ Corrected RX equalization DC gain in transceiver Reconfiguration Controller chapter. It
should be 0–4.
■ Corrected serialization factor column in Low Latency PHY IP Core chapter.
Introduction
May 2011 1.2
■ Added simulation section.
■ Revised Figure 1–1 on page 1–2 to show the Transceiver Reconfiguration Controller as a
separately instantiated IP core.
■ Added statement saying that the transceiver PHY IP cores do not support the NativeLink
feature of the Quartus II software.
■ Revised reset section.
Getting Started
May 2011 1.2
■ No changes from previous release.
10GBASE-R PHY Transceiver
May 2011 1.2
■ Corrected frequency of pll_ref_clk . Should be 644.53125 MHz, not 644.53725 MHz.
■ Renamed reconfig_fromgxb and reconfig_togxb reconfig_from_xcvr and
reconfig_to_xcvr , respectively.
XAUI PHY Transceiver
Date Version Changes Made SPR