User guide

Info–4 Additional InformationAdditional Information
Revision History
Altera Transceiver PHY IP Core March 2012 Altera Corporation
User Guide
November
2011
1.3
■ Added pll_powerdown bit (bit[0] of 0x044) for manual reset control. You must assert this
bit for 1 μs for Gen 2 operation.
■ Added PLL type and base data rate parameters.
■ Updated QSF settings to include text strings used to assign values and location of the
assignment which is either a pin or PLL.
Custom Transceiver PHY
November
2011
1.3
■ Added Arria V and Cyclone V support.
■ Added base data rate, lane rate, input clock frequency, and PLL type parameters.
■ Revised reset options. The 2 options for reset are now the embedded reset controller or a
user-specified reset logic.
■ Updated QSF settings to include text strings used to assign values and location of the
assignment which is either a pin or PLL.
Low Latency PHY
November
2011
1.3
■ Added base data rate, lane rate, input clock frequency, and PLL type parameters.
■ Updated QSF settings to include text strings used to assign values and location of the
assignment which is either a pin or PLL.
■ Revised reset options. The 2 options for reset are now the embedded reset controller or a
user-specified reset logic.
Deterministic Latency
November
2011
1.3
■ Initial release of this chapter.
Transceiver Reconfiguration Controller
November
2011
1.3
■ Added MIF support to allow transceiver reconfiguration from a .mif file that may contain
updates to multiple settings.
■ Added support for the following features:
■ EyeQ
■ AEQ
■ AEQ
■ ATX tuning
■ PLL reconfiguration
■ DC gain and four-stage linear equalization for the RX channels
■ Removed Stratix IV device support.
■ Changed frequency range of phy_mgmt_clk to 100-125 MHz.
Date Version Changes Made SPR