User guide
Info–2 Additional InformationAdditional Information
Revision History
Altera Transceiver PHY IP Core March 2012 Altera Corporation
User Guide
Transceiver Reconfiguration Controller
February 2012 1.5
■ Added DFE.
Introduction
December
2011
1.4
■ Revised discussion of embedded reset controller to include the fact that this reset controller
can be disabled for some transceiver PHYs.
10GBASE-R
December
2011
1.4
■ Removed description of calibration block powerdown register (0x021) which is not available
for this transceiver PHY.
■ Changed definition of
phy_mgmt_clk_reset
. This signal is active high and level sensitive.
XAUI
December
2011
1.4
■ Changed definition of
phy_mgmt_clk_reset
. This signal is active high and level sensitive.
■ Added Arria II GX to device support table.
Interlaken
December
2011
1.4
■ Changed access mode for RX equalization, pre-CDR reverse serial loopback, and post-CDR
reverse serial loopback to write only (WO).
■ Removed optional
rx_sync_word_err
,
rx_scrm_err
, and
rx_framing_err
status bits.
■ Changed definition of
phy_mgmt_clk_reset
. This signal is active high and level sensitive.
PHY IP Core for PCI Express (PIPE)
December
2011
1.4
■ Changed definition of
phy_mgmt_clk_reset
. This signal is active high and level sensitive.
Custom
December
2011
1.4
■ Added ×N and feedback compensation options for bonded clocks.
■ Added Enable Channel Interface parameter which is required for dynamic reconfiguration
of transceivers.
■ Corrected formulas for signal width in top-level signals figure.
■ Changed definition of
phy_mgmt_clk_reset
. This signal is active high and level sensitive.
Low Latency PHY
December
2011
1.4
■ Added option to disable the embedded reset controller to allow you to create your own reset
sequence.
■ Added ×N and feedback compensation options for bonded clocks.
■ Fixed name of
phy_mgmt_reset
signal. Should be phy_mgmt_clk_reset. Also, a positive
edge on this signal initiates a reset.
■ Added Enable Channel Interface parameter which is required for dynamic reconfiguration
of transceivers.
■ Corrected formulas for signal width in top-level signals figure.
■ Changed definition of
phy_mgmt_clk_reset
. This signal is active high and level sensitive.
Deterministic Latency PHY
December
2011
1.4
■ Removed Enable tx_clkout feedback path for TX PLL from the General Options tab of the
Deterministic Latency PHY IP Core GUI. This option is unavailable in 11.1 and 11.1 SP1.
■ Changed definition of
phy_mgmt_clk_reset
. This signal is active high and level sensitive.
Date Version Changes Made SPR