User guide

3–4 Chapter 3: 10GBASE-R PHY IP Core

Parameter Settings

Altera Transceiver PHY IP Core March 2012 Altera Corporation

User Guide

Stratix V Devices

For Stratix V devices, the PCS and PMA are both implemented in hard logic; the

10GBASE-R transceiver PHY requires less than 1% of FPGA resources.

Table 3–4 lists the total latency for an Ethernet packet with a 9600 byte payload and an

inter-packet gap of 12 characters. The latency includes the number of cycles to

transmit the payload from the TX XGMII interface, through the TX PCS and PMA,

looping back through the RX PMA and PCS to the RX XGMII interface. (Figure 3–5 on

page 3–16 illustrates this datapath.)

1 It latency is critical, Altera recommends designing your own soft 10GBASE-R PCS

and connecting to the “Low Latency PHY IP Core” .

Parameter Settings

To configure the 10GBASE-R PHY IP core in the parameter editor, click Installed

Plug-Ins > Interfaces >Ethernet> 10GBASE-R PHY v11.1. The 10GBASE-R PHY IP

core is available for the Stratix IV or Stratix V device family.

General Options

This section describes the 10GBASE-R PHY parameters, which you can set using the

parameter editor. Table 3–5 lists the settings available on General Options tab.

Table 3–4. Latency

PPM Difference Cycles

0 PPM 35

-200 PPM 35

+200 PPM 42

Table 3–5. General Options (Part 1 of 2)

Name Value Description

General Options

Device family

Stratix IV GT

Stratix V

Specifies the target device.

Number of channels

–

The total number of 10GBASE-R PHY channels.

Mode of operation

Duplex

TX only

RX only

Stratix V devices allow duplex, TX, or RX mode. Stratix IV GX devices

only support duplex mode.