User guide

11–12 Chapter 11: Migrating from Stratix IV to Stratix V Devices
Custom PHY
Altera Transceiver PHY IP Core March 2012 Altera Corporation
User Guide
High Speed Serial I/O
rx_datain rx_serial_data [<n>-1:0]
tx_dataout tx_serial_data [<n>-1:0]
rx_freqlocked rx_is_lockedtodata [<n>-1:0]
Transceiver Control and Status Signals
gxb_powerdown phy_mgmt_clk_reset
rx_dataoutfull
—
tx_dataoutfull —
rx_pll_locked
There are both pll_locked and
rx_pll_clocked in Stratix IV. Stratix V only has
pll_locked.
rx_clkout
These signals are now available as control and
status registers. Refer to “Register Descriptions”
on page 7–21.
rx_phase_comp_fifo_error
rx_seriallpbken
tx_phase_comp_fifo_error
tx_invpolarity
Transceiver Reconfiguration
reconfig_togxb[3:0] reconfig_to_xcvr variable
reconfig_fromgxb[16:0] reconfig_from_xcvr variable
Note to Table 11–7:
(1) <n> = the number of lanes. <d> = the total deserialization factor from the pin to the FPGA fabric.
Table 11–7. Custom PHY Correspondences between Stratix IV GX Device and Stratix V Device Signals