User guide

Chapter 11: Migrating from Stratix IV to Stratix V Devices 11–11
Custom PHY
March 2012 Altera Corporation Altera Transceiver PHY IP Core
User Guide
Port Differences
Table 11–5 lists the differences between the top-level signals in Stratix IV GX and
Stratix V GX/GS devices.
What is the word alignment pattern lengthWord aligner pattern length
Protocol Settings—Rate match/Byte order Rate Match
What is the 20-bit rate match pattern1
(usually used for +ve disparity pattern)
Rate match insertion/deletion +ve disparity pattern
What is the 20-bit rate match pattern1
(usually used for -ve disparity pattern)
Rat
e match insertion/deletion -ve disparity pattern
Protocol Settings—Rate match/Byte order Byte Order
What is the byte ordering patternByte ordering pattern
Note to Table 11–6:
(1) This parameter is on the Datapath tab.
Table 11–6. Comparison of ALTGX Megafunction and Custom PHY Parameters (Part 2 of 2)
Table 11–7. Custom PHY Correspondences between Stratix IV GX Device and Stratix V Device Signals
ALTGX Custom PHY Width
Avalon MM Management Interface
Not available
phy_mgmt_clk_reset 1
phy_mgmt_clk 1
phy_mgmt_address 8
phy_mgmt_read 1
phy_mgmt_readdata 32
phy_mgmt_write 1
phy_mgmt_writedata 32
Clocks
cal_blk_clk
These signals are included in the
reconfig_to_xcvr bus
reconfig_clk
pll_inclk pll_ref_clk [<p>-1:0]
rx_coreclk rx_coreclkin
tx_coreclk tx_coreclkin
Avalon-ST TX Interface
tx_datain tx_parallel_data [<d><n>-1:0]
tx_ctrlenable tx_datak [<d><n>-1:0]
rx_ctrldetect rx_datak [<d><n>-1:0]
Avalon-ST RX Interface
rx_dataout rx_parallel_data [<d><n>-1:0]
rx_runningdisp rx_runningdisp [<d/8><n>-1:0]
rx_enabyteord rx_enabyteord [<n>-1:0]