User guide

Chapter 11: Migrating from Stratix IV to Stratix V Devices 11–9
PHY IP Core for PCI Express PHY (PIPE)
March 2012 Altera Corporation Altera Transceiver PHY IP Core
User Guide
rx_locktodata
These signals are now available as control and
status registers. Refer to the “Register
Descriptions” under “Avalon-MM PHY
Management Interface” on page 6–14
[
<n> -1:0]
rx_locktorefclk [ <n> -1:0]
tx_invpolarity [ <n> -1:0]
rx_errdetect [( <d> /8)* <n> -1:0]
rx_disperr [( <d> /8)* <n> -1:0]
rx_patterndetect [( <d> /8)* <n> -1:0]
tx_phase_comp_fifo_error [ <n> -1:0]
rx_phase_comp_fifo_error [ <n> -1:0]
rx_signaldetect [ <n> -1:0]
rx_rlv [ <n> -1:0]
rx_datain rx_serial_data [ <n> -1:0]
tx_dataout tx_serial_data [ <n> -1:0]
Reconfiguration
cal_blk_clk
These signals are included in the
reconfig_to_xcvr bus
1
reconfig_clk 1
fixedclk 1
reconfig_togxb reconfig_to_xcvr variable
reconfig_fromgxb reconfig_from_xcvr variable
Avalon MM Management Interface
Not available
phy_mgmt_clk_reset 1
phy_mgmt_clk 1
phy_mgmt_address [8:0]
phy_mgmt_read 1
phy_mgmt_readdata [31:0]
phy_mgmt_write 1
phy_mgmt_writedata [31:0]
Note to Table 11–5:
(1) <n> = the number of lanes. <d> = the total deserialization factor from the pin to the FPGA fabric.
Table 11–5. PCIe PHY (PIPE) Correspondence between Stratix IV GX Device and Stratix V Device Signals (Part 3 of 3)
(1)
Stratix IV GX Device Signal Name Stratix V Device Signal Name Width