User guide

11–8 Chapter 11: Migrating from Stratix IV to Stratix V Devices
PHY IP Core for PCI Express PHY (PIPE)
Altera Transceiver PHY IP Core March 2012 Altera Corporation
User Guide
pll_powerdown These signals are now available as control and
status registers. Refer to the “Avalon-MM PHY
Management Interface” on page 6–14 and “PCI
Express PHY (PIPE) IP Core Registers” on
page 6–14
1
cal_blk_powerdown 1
Not available
tx_ready (reset control status) 1
Not available
rx_ready (reset curl status) 1
PIPE interface Ports
tx_datain pipe_txdata [ <n><d> -1:0]
tx_ctrlenable pipe_txdatak [( <d> /8)* <n> -1:0]
tx_detectrxloop pipe_txdetectrx_loopback [ <n> -1:0]
tx_forcedispcompliance pipe_txcompliance [ <n> -1:0]
tx_forceelecidle pipe_txelecidle [ <n> -1:0]
txswing pipe_txswing [ <n> -1:0]
tx_pipedeemph[0] pipe_txdeemph [ <n> -1:0]
tx_pipemargin[2:0] pipe_txmargin [3 <n> -1:0]
rateswitch[0] pipe_rate[1:0] [ <n> -1:0]
powerdn pipe_powerdown [2 <n> -1:0]
rx_elecidleinfersel pipe_eidleinfersel [3 <n> -1:0]
rx_dataout pipe_rxdata [ <n> -* <d> -1:0]
rx_ctrldetect pipe_rxdatak [( <d> /8)* <n> -1:0]
pipedatavalid pipe_rxvalid [ <n> -1:0]
pipe8b10binvpolarity pipe_rxpolarity [ <n> -1:0]
pipeelecidle pipe_rxelecidle [ <n> -1:0]
pipephydonestatus pipe_phystatus [ <n> -1:0]
pipestatus pipe_rxstatus [3 <n> -1:0]
Non-PIPE Ports
rx_pll_locked rx_is_lockedtoref [ <n> --1:0]
rx_freqlocked rx_is_lockedtodata [ <n> --1:0]
pll_locked pll_locked 1
rx_syncstatus rx_syncstatus (also management interface) [( <d> /8)* <n> -1:0]
Table 11–5. PCIe PHY (PIPE) Correspondence between Stratix IV GX Device and Stratix V Device Signals (Part 2 of 3)
(1)
Stratix IV GX Device Signal Name Stratix V Device Signal Name Width