User guide

Chapter 11: Migrating from Stratix IV to Stratix V Devices 11–7
PHY IP Core for PCI Express PHY (PIPE)
March 2012 Altera Corporation Altera Transceiver PHY IP Core
User Guide
Port Differences
Table 11–5 lists the differences between the top-level signals in Stratix IV GX and
Stratix V GX/GS devices. PIPE standard ports remain, but are now prefixed with
pipe_ . Clocking options are simplified to match the PIPE 2.0 specification.
Train receiver CDR from pll_inclk (false)
Not available in MegaWizard Interface
Use assignment editor to
make these assignments
TX PLL bandwidth mode (Auto)
RX CDR bandwidth mode (Auto)
Acceptable PPM threshold (
±300)
Analog Power(VCCA_L/R) (Auto)
Reverse loopback option (No loopback)
Enable static equalizer control (false)
DC gain (1)
RX Vcm (0.82)
Force signal detection (Off)
Signal Detect threshold (4)
Use external receiver termination (Off)
RX term (100)
Transmitter buffer power(VCCH) (1.5)
TX Vcm (0.65)
Use external transmitter termination (Off)
TX Rterm (100)
VCO control setting (5)
Pre-emphasis 1st post tap (18)
Not available in MegaWizard Interface
Use assignment editor to
make these assignments
Pre-tap (0)
2nd post tap (0)
DPRIO - V
OD
, Pre-em, Eq and EyeQ (Off)
DPRIO - Channel and TX PLL Reconfig (Off)
Table 11–4. Comparison of ALTGX Megafunction and PHY IP Core for PCI Express PHY (PIPE) Parameters (Part 2 of 2)
ALTGX Parameter Name (Default Value) PCI Express PHY (PIPE) Parameter Name Comments
Table 11–5. PCIe PHY (PIPE) Correspondence between Stratix IV GX Device and Stratix V Device Signals (Part 1 of 3)
(1)
Stratix IV GX Device Signal Name Stratix V Device Signal Name Width
Reference Clocks and Resets
pll_inclk pll_ref_clk 1
rx_cruclk Not available [ <n> -1:0]
tx_coreclk Not available [ <n> -1:0]
rx_coreclk Not available [ <n> -1:0]
tx_clkout/coreclkout pipe_pclk 1