User guide

11–4 Chapter 11: Migrating from Stratix IV to Stratix V Devices
XAUI PHY
Altera Transceiver PHY IP Core March 2012 Altera Corporation
User Guide
Port Differences
Table 11–5 lists the differences between the top-level signals in Stratix IV GX and
Stratix V GX/GS devices.
Acceptable PPM threshold between receiver CDR VCO
and receiver input reference clock (
±1000)
Not available as parameters in
the MegaWizard interface
Use assignment editor to
make these assignments
Analog power (Auto)
Loopback option (No loopback)
Enable static equalizer control (Off)
DC gain (0)
Receiver common mode voltage (0.82v)
Use external receiver termination (Off)
Receiver termination resistance (100 ohms)
Transmitter buffer power (1.5v)
Transmitter common mode voltage
(0.65v)
Use external transmitter termination (Off)
Transmitter termination resistance (100 ohms)
VOD setting (4)
Preemphasis 1
st
post-tap (0)
Preemphasis pre-tap setting (0)
Preemphasis second post-tap setting (0)
Analog controls (Off)
Enable ADCE (Off)
Not available as parameters in
the MegaWizard interface
Not available in 10.0
Enable channel and transmitter PLL reconfig (Off)
Starting channel number (0) No longer required
Automatically set to 0. The
Quartus II software handles
lane assignments
Enable run length violation checking with run length of
(40)
Not available as parameters in
the MegaWizard interface
Use assignment editor
Enable transmitter bit reversal
(Off)
Word alignment pattern length (10)
Table 11–2. Comparison of ALTGX Megafunction and XAUI PHY Parameters (Part 2 of 2)
ALTGX Parameter Name (Default Value) XAUI PHY Parameter Name Comments
Table 11–3. Correspondences between XAUI PHY Stratix IV GX and Stratix V Device Signals (Part 1 of 3)
(1)
Stratix IV GX Devices Stratix V Devices
Signal Name Width Signal Name Width
Reference Clocks and Resets
pll_inclk 1 refclk 1
rx_cruclk [<n> -1:0] Not available —
coreclkout 1 xgmii_rx_clk 1
rx_coreclk [<n> – 1:0] Not available —