User guide

Chapter 3: 10GBASE-R PHY IP Core 3–3
Device Family Support
March 2012 Altera Corporation Altera Transceiver PHY IP Core
User Guide
Device Family Support
IP cores provide either final or preliminary support for target Altera device families.
These terms have the following definitions:
■ Final support—Verified with final timing models for this device.
■ Preliminary support—Verified with preliminary timing models for this device.
Table 3–2 shows the level of support offered by the 10GBASE-R IP core for Altera
device families.
f For speed grade information, refer to “Transceiver Performance Specifications” in the
DC and Switching Characteristics chapter in the Stratix IV Handbook for Stratix IV
devices or DC and Switching Characteristics for Stratix V Devices in the Stratix V Device
Handbook for Stratix V devices.
Performance and Resource Utilization
This section provides information on performance and resource utilization for
Stratix IV and Stratix V devices.
Stratix IV Devices
Table 3–3 shows the typical expected device resource utilization for duplex channels
using the current version of the Quartus II software targeting a Stratix IV GT device.
The numbers of combinational ALUTs, logic registers, and memory bits are rounded
to the nearest 100.
Vendor ID 6AF7
Note to Table 3–1:
(1) No ordering codes or license files are required for Stratix V devices.
Table 3–1. 10GBASE-R Release Information (Part 2 of 2)
Item Description
Table 3–2. Device Family Support
Device Family Support
Stratix IV GT devices–Soft PCS and PMA Final
Stratix V devices–Hard PCS and PMA Preliminary–C2 Speed Grade
Other device families No support
Table 3–3. 10GBASE-R PHY Performance and Resource Utilization—Stratix IV GT Device
Channels Combinational ALUTs Logic Registers (Bits) Memory Bits
1 5200 4100 4700
4 15600 1300 18800
10 38100 32100 47500