User guide
10–40 Chapter 10: Transceiver Reconfiguration Controller
Loopback Modes
Altera Transceiver PHY IP Core March 2012 Altera Corporation
User Guide
Figure 10–15 shows the datapath for serial loopback. The data from the FPGA fabric
passes through the TX channel and is looped back to the RX channel, bypassing the
RX buffer. The received data is available to the FPGA logic for verification. Using the
serial loopback option, you can check the operation of all enabled PCS and PMA
functional blocks in the TX and RX channels. When serial loopback is enabled, the TX
channel sends the data to both the
tx_serial_data
output port and the RX channel.
Figure 10–15. Serial Loopback
Tx PCS
Rx PCS
FPGA
Fabric
Tx PMA
tx_dataout
Serializer
Rx PMA
Serial
loopback
De-
serializer
To FPGA fabric
for verication
Transceiver